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Can channel 5 set to counter clear of timer control register of MTU2?

Latest Updated:03/26/2009

Question:

CCLR bit (counter clear bit) doesn’t exist in the timer control register of MTU2 (TCRU/V/W_5) channel 5. Can channel 5 set to counter clear?

Answer:

Because the configuration of channel 5 of MTU2 is different from the other channel, it sets it by another register (Timer compare match clear register).

Please refer to the section of MTU2 of the hardware manual “Register Descriptions (timer compare match clear register (TCNTCMPC))”.

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