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"How long does it take from inputting the BREQ# to releasing the bus? "

Latest Updated:03/21/2012

Question:

How long does it take from inputting the bus request signal (BREQ#) to releasing the bus?

Answer:

If the bus cycle is not executed at the time of bus request (BREQ#), the bus is released within 1.5 cycle in minimum (bus clock=CK). Refer to below.
After sampling the BREQ#=Low at the fall of CK, the address bus signal and data bus signal enter in high-impedance state at the next rise of CK.
-- 0.5 cycle has passed at this point.
In the next stage, the bus enable signal (BACK#) is asserted at low level at the time of the fall of CK.
--1 cycle has passed at this point.
Then at the next rise of CK, other bus control signals enter in high impedance.
--1.5 cycles have passed at this point.
Attention is required; even when the bus cycle does not seem to be executed, the bus cycle may start internally. For details, refer to the Section "Bus Arbitration", Part "Operation", Chapter "Bus State Controller"of User's Manual: Hardware.
Suitable Products
SH7285, SH7286
SH7243
SH7214, SH7216
SH7231
SH7239, SH7237
SH7211