Please check the following points.
- The interrupt priority level select bits (IPR) in the interrupt priority register (IPR) is set to a higher value than the processor interrupt priority level (IPL) in the processor status word (PSW).
- The interrupt request enable bit (IEN) in the interrupt request enable register (IER) is enabled.
- The interrupt enable bit of the peripheral module is enabled.
- If an input signal is being used as the interrupt trigger: The input buffer control register (ICR) of the corresponding port is enabled.
- A module stop bit in a module stop control register (MSTPCRA, MSTPCRB, or MSTPCRC) of the corresponding peripheral module is set to 0.
For more information, please refer to the "Interrupt Control Unit", "I/O Ports", and "Power-Down Modes" chapters, as well as the sections on their peripheral modules, in the hardware manual.