When BCLK output has been set, although it will automatically stop in software standby mode and deep software standby mode and go high, it will not stop in sleep mode and all-module clock stop mode.
BCLK output needs to be stopped before entering sleep mode and all-module clock stop mode.
BCLK output can be controlled by the BCLK output stop bit (PSTOP1) in the system clock control register (SCKCR) and the data direction register (P5.DDR.B3 bit) of the P53 port.
After BCLK is stopped, clearing the P5.DDR.B3 bit of P53 to 0 turns it into an I/O port.
For details, please refer to External Bus Clock (BCLK) in the Clock Generation Circuit chapter and BCLK Output Control in the Low Power Consumption chapter of the hardware manual.