When DMA accesses external space do ICIS0 & ICIS1 influence bus timing ?
Latest Updated:03/18/2009
Question:
Bits ICISO & ICIS1 in the BCR register of the H8/3067 import idle cycles . When the DMA controller accesses external space do ICIS0 & ICIS1 influence bus timing ?
Answer:
The Bus Controller still operates during DMAC operation. If idle cycle insertion is designated by BCR the cycle is inserted at DMAC start up.
Suitable Products
| H8/300H |